1. Field of the Invention
The present invention relates to a semiconductor integrated circuit using an AVS (Adaptive Voltage Scaling) technique or a DVS (Dynamic Voltage Scaling) technique suitable for reducing an electric power consumption.
2. Description of the Related Art
Since a pace has been continuously kept for ten years or more that improves a degree of integration of a semiconductor to four times as high as that of a first year in three years, the scale of a semiconductor integrated circuit is enormously large and a method for constructing chips of the semiconductor integrated circuit has been greatly changed.
FIG. 15 is a block diagram showing the structure of a system LSI. In FIG. 15, a semiconductor integrated circuit 600 includes a general-purpose CPU 611, a DSP (Digital Signal Processor) 612, a special-purpose circuit 613, a special-purpose circuit 614, an SDRAM (Synchronous Dynamic TAM) control circuit 615 and a DMA (Direct Memory Access) controller 616. These members are mutually connected through a common bus 617. The CPU 611 and the DSP 612 respectively have an inner memory 611a and an inner memory 612a in inner parts thereof. In the semiconductor integrated circuit 500, an SDRAM 618 of a large capacity is ordinarily prepared in an external part.
Even at the present time, there is a possibility that a request for functions mounted on the semiconductor integrated circuit rapidly changes every day. When a part of the functions is formed as the special-purpose circuit 613 or the special-purpose circuit 614 as shown in FIG. 15, such a change of the request may not be possibly rapidly met.
Therefore, at the present stage, as shown in FIG. 16, functions mainly composed of a calculating function except the general-purpose CPU are formed in the structures of “multifunction DSP+an expanded function” and a specification that may possibly change is progressively met by software on the multifunction DSP.
FIG. 16 is a block diagram showing such a system LSI. In FIG. 16, a semiconductor integrated circuit 700 includes a general-purpose CPU 711, a calculating function part 723 having a multifunction DSP 721 and an expanded function 722, a calculating function part 726 having a multifunction part 724 and an expanded function 725, an SDRAM control circuit 715, a DMA controller 716, local buses 727 to 729 arranged in the side of the function parts respectively, a global bus 730 arranged in the side of the SDRAM control circuit 715 and the DMA controller 716 and bus bridges 731 to 733 for connecting the local buses 727 to 729 to the global bus 730. The multifunction DSP 721 has an inner memory 721a. In the structures of the buses, the local buses 727 to 729 are allocated to the function parts respectively. In the SDRAM control circuit 715 side, the global bus 730 is arranged. Between the local buses 727 to 729 and the global bus 730, the bus bridges 731 to 733 are arranged.
With the progress of a semiconductor process in the future, when many functions are increasingly mounted on the semiconductor integrated circuit, the structure of the semiconductor integrated circuit will be further changed as shown in FIG. 17.
FIG. 17 is a block diagram showing another structure of a system LSI. In FIG. 17, a semiconductor integrated circuit 800 includes one general-purpose CPU 811, four general purpose calculating processors 841 to 844 having inner memories 841a to 844a, an SDRAM control circuit 815, a DMA controller 816, an I/O control circuit 845 for controlling a peripheral I/O group 860, a local bus 846 arranged in the side of the CPU 811 and the 1/0 control circuit 845, local buses 847 to 850 arranged in the side of the general-purpose calculating processors 841 to 844, a global bus 851 arranged between the local bus 846 and the local buses 847 to 850, bus bridges 852 to 855 for connecting the local buses 847 to 850 to the global bus 851 and a bus bridge 856 for connecting the local bus 846 to the global bus 851.
In the semiconductor integrated circuit 800, the one general-purpose CPU 811 and several (four to eight or so) general-purpose calculating processors 841 to 844 are connected together through the local buses 846 to 850, the global bus 851 and the bus bridges 852 to 856. An SDRAM 818 of a large capacity is arranged in an external part. The SDRAM control circuit 815 adjusts the general-purpose CPU 811, the several calculating processors 841 to 844 and the DMA controller 816 or the like relative to the SDRAM 818.
As described above, when the degree of integration of the semiconductor integrated circuit is enhanced, a problem of a consumed electric power arises that increases during an operation or a stand-by as the most serious problem. As a method for solving this problem, there is a DVS (Dynamic Voltage Scaling) technique or an AVS (Adaptive Voltage Scaling) technique as the technique that most attracts an attention. Since the contents of these techniques are described in detail in below-described documents (for instance, Patent Documents 1 and 2 and Non-Patent Documents 1 and 2), an explanation thereof will be omitted.
However, the above-described usual semiconductor integrated circuits have problems as described below.
According to the Non-Patent Document 1, the AVS technique has a great restricted matter under existing circumstances. The present AVS technique is adopted on the assumption that this technique is used for all chips. In this case, all the chips change source voltages and system clock frequencies corresponding thereto at the same time. Namely, in this system, the source voltages of the chips and the system clock frequencies change on the basis of a time base, and the CPU controls the source voltage of the chip to be raised (for instance, VDD=1.5 V) and the system clock frequency to be also raised (for instance, fclk=400 MHz) when an amount of a load of a work is large. Further, when an amount of a load of the work is small, the CPU controls the source voltage of the chip to be lowered (for instance, VDD=1.0 V) and the system clock frequency to be also lowered (for instance, fclk=200 MHz). In such a way, the electric power consumed in the chips can be reduced. Ordinarily, in the system LSI, various kinds of functional blocks such as a video signal processing block, an audio signal processing block, a control signal processing block or the like are provided and a large difference exists in an amount of a load of a work required for a process between these functional blocks.
As a related art that tries to solve the above-described problem, the Non-Patent Document 2 is exemplified. Here, the source voltage of the audio signal processing block can be selected from 0.9 V/1.2 V and the system clock frequency can be selected from 90 MHz/180 MHz, however, for other blocks than the audio signal processing block (here, the video signal processing block or the like is provided), the source voltage is fixed to 1.2 V and the system clock frequency is fixed to 180 MHz.
In accordance with the above-description, in the functional blocks respectively, to what source voltage the source voltage is set and to what operating frequency the frequency is set correspondingly to the contents of the works respectively for a multifunction DSP are determined in accordance with a previous minute and careful simulation. However, when the inner circuit of each block of the multifunction DSP is investigated, various delay paths exist in the circuit. The value of the source voltage necessary for executing a specific work in the multifunction DSP is determined by a group of delay paths called as a critical path among the various delay paths existing in the functional block. Assuming that the operating frequency is constant while a certain work is carried out, the source voltage value needs to have a margin in order to provide a margin for the operation of the multifunction DSP.
When the consumed electric power of the multifunction DSP is tried to be reduced, the source voltage value of the multifunction DSP to be set may be set to the lowest value that can pass at all costs the critical path whose delay value is the largest. However, it is very difficult to determine such a subtle setting even by a previous minute and careful simulation.
As a usual technique for realizing the delicate setting of the source voltage value, a canary flip-flop shown in FIG. 18 that is disclosed in Patent Document 3 is devised. In FIG. 18, a signal 901 initially synchronizes with a clock signal 902 and is taken into a flip-flop 903. In a next clock period, the signal is delayed by a combined circuit 904 and then taken into a flip-flop 905 (refer it to as a “main FF 905”, hereinafter.). A signal obtained by delaying the signal that is delayed by the combined circuit 904 by a specific time by a delay element 907 is taken to a flop-flop 908 (refer it to as a “canary FF 908”, hereinafter.). The signal from the main FF 905 is compared with the signal from the canary FF 908 by a comparison circuit 909 formed with an Exclusive-OR circuit. When values held by the main FF 905 and the canary FF 908 are different from each other, this indicates that when the signal 901 is delayed by a delay value of the delay element 907 from a present state, the signal 901 generates a malfunction. That is, a timing error can be anticipated in accordance with the structure of the canary FF. When an output of the comparison circuit 909 is “1” by the delay value of the delay element 907 corresponding to a necessary margin, this indicates that a sufficient margin is not provided for the source voltage value of the block of the multifunction DSP from the viewpoint of the margin. Therefore, a control needs to be carried out so as to raise the source voltage value VDD 950 of the block of the multifunction DSP.
Patent Document 1: U.S. Pat. No. 5,745,375
Patent Document 2: U.S. Pat. No. 6,868,503
Patent Document 3: JP-A-2006-60086
Patent Document 4: JP-A-2007-249308
Non-Patent Document 1: “A Combined Hardware-Software Approach for Low-Power SoC: Applying Adaptive Voltage Scaling and Intelligent Energy management Software”, Design 2003 (System-on-Chip and ASIC Design Conference)
Non-Patent Document 2: “An H. 264/MPEG-4 Audio/Visual Codec LSI with Module-Wise Dynamic Voltage/Frequency Scaling”, ISSCC2005 Dig. Tech, Papers, pp. 132-133
Non-Patent Document 3: T. Sato and Y Kunitake “A Simple Flip-Flop Circuit for Typical-Case Designs for DFM” 8 th International Symposium on Quality Electronic Design, 2007
The control of the multifunctional DSP block using the above-described canary FF is an effective method for setting the source voltage value that can be hardly determined by a previous minute and careful simulation, however, this method has below-described problems.
(1) Problem 1
In the Non-Patent Document 3, when the output of the comparison circuit 909 is “1”, this indicates that a sufficient margin is not provided for the source voltage value of the block of the multifunction DSP. Therefore, such a control is carried out as to raise the source voltage value VDD 950 of the block of the multifunction DSP. In the Non-Patent Document 3, the source voltage of the entire part of the block of the multifunction DSP is raised. Accordingly, the source voltages of most of circuits that are not the critical path are also raised, which is not preferable in view of the reduction of the consumed electric power of the semiconductor integrated circuit.
(2) Problem 2
In the structure for controlling the source voltage value of the block of the multifunction DSP using the canary FF disclosed in the Non-patent Document 3, even when the margin of the critical path is desired to be set to a value between 10% and 20%, it cannot be realized.
As described above, in controlling the source voltage value of the block of the multifunction DSP using the canary FF, the two large problems as mentioned above arise.